Frequency divider with shift register and modulator

Abstract

A non-integer frequency divider is provided that can perform switching of a frequency division ratio setting at high speed in order to improve the phase noise of frequency synthesizers and raise their response speeds. The frequency divider is a non-integer frequency divider that performs frequency division with frequency division ratios that contain decimal fraction, and includes a first frequency divider which can be set to a number of integer frequency division ratios; a second frequency divider (i.e., a shift register); a bit selector; a CA value generator; and a .SIGMA..DELTA. modulator. Non-integer frequency division is realized by switching the settings of the frequency division ratio and the period number of the frequency division output signal of the first frequency divider and the setting of the frequency division ratio of the second frequency divider. In the prior art, a programmable counter was used as the second frequency divider, but since the speed with which it switched settings was slow, it was not possible to satisfy the demands of frequency synthesizers. The use of a shift register for the second frequency divider enables both speed and noise improvements.