The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 1998

Filed:

Jan. 31, 1997
Applicant:
Inventors:

Ronald Dekker, Eindhoven, NL;

Henricus G Maas, Eindhoven, NL;

Martinus P Versleijen, Eindhoven, NL;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
438113 ; 438125 ; 438461 ; 438611 ; 257522 ;
Abstract

The invention relates to a method of manufacturing a semiconductor device (1) for surface mounting. Such a method is known, whereby such a semiconductor device is manufactured in that a semiconductor body with a semiconductor element is mounted on a metal lead frame with metal package leads, after which contact surfaces of the semiconductor element are connected to the package leads by means of bonding wires. It is found that semiconductor devices of small dimensions are difficult to realize by this known method, while in addition the manufacture of integrated circuits with very many package leads is comparatively expensive owing to the many connections which are to be made between the integrated circuits and the package leads. According to the invention, the semiconductor devices are packaged while they are still on a slice of semiconductor material, while the package leads are formed from the semiconductor material. In the method according to the invention, the semiconductor devices are manufactured without the necessity of a lead frame, bonding wires, or metal package leads. Thanks to the IC technologies at the wafer level, such as photolithography, etching, etc., the method according to the invention renders possible semiconductor devices of very small dimensions. In addition, integrated circuits with very many package leads can be manufactured in a simple manner without additional steps being necessary. The method according to the invention is thus comparatively inexpensive.


Find Patent Forward Citations

Loading…