Method of making eeprom cell with improved coupling ratio

Abstract

A method of forming EEPROM cells. The method includes forming a tunnel oxide layer on a wafer and forming floating gates on the tunnel oxide layer with the floating gate having sidewalls. Isolation regions may be formed adjacent the sidewalls. A conformal ONO layer of dielectric is formed on the floating gate and sidewalls, using Chemical Vapor Deposition. Next, a selective etch material layer is deposited on the wafer over the conformal dielectric layer. A polish stop layer is deposited on the wafer over the selective etch material layer to define an upper polishing surface above the floating gate. The exposed polish stop layer and underlying selective etch material are removed by depositing an oxide layer on the polish stop layer and then polishing the deposited layer coplanar with the polish stop layer which is an upper polishing surface above the floating gates. Exposed portions of the polish stop layer are removed to expose the selective etch layer above the floating gates and above sidewall regions adjacent the sidewalls. Then, the exposed selective etch layer is removed, exposing the conformal dielectric layer. Finally, a control gate may be formed by depositing a control gate layer above the floating gate and within the sidewall region and patterning the control gate layer. The patterned control gates extend over the floating gate and along the floating gate sidewalls. The control gate-floating gate capacitor area includes the floating gate sidewalls.