The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 1998
Filed:
May. 23, 1997
Mario Nemirovsky, San Jose, CA (US);
Alexander Perez, Sunnyvale, CA (US);
Robert James Divivier, San Jose, CA (US);
Narendra Sankar, Sunnyvale, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
An apparatus and method for efficiently generating the consecutive addresses needed to access misaligned or doubleword length data stored in the memory of a general purpose microprocessor. The apparatus shares the address generation operations between a small 3 bit adder, typically contained in the bus unit, and the execution unit. Control logic is used to determine whether a data misalignment situation exists based on the length of the data which is to be retrieved and the starting address of the data. When misalignment is indicated, the control unit acts to assign the address calculations to either the 3 bit adder alone or the execution unit together with the 3 bit adder depending upon how much the present address must be incremented to obtain the new addresses.