Circuit to indicate phase lock in a multimode phase lock loop with

Abstract

A lock detection circuit for a phase lock loop circuit having a phase lock loop circuit, generally a series circuit of a detector, a filter and a VCO with a PLL input terminal and an output terminal. A test circuit is coupled to the phase lock loop and includes a signal generator responsive to the presence of an input signal on the input terminal to inject a test signal into the phase lock loop. The signal generator is preferably a low frequency oscillator wherein the term 'low' is defined to mean any frequency from a few hertz up to gigahertz and generally a few kilohertz, as long as this frequency is at least about an order of magnitude less than the frequencies to be encountered at the RF input to the PLL. The signal generated by the signal generator is compared with the signal injected into the phase lock loop which is generally injected ahead of the loop filter. When there is a substantial match, particularly in frequency and phase of the injected signal, it is assumed that the PLL circuit is operating properly and the PLL output is then permitted to be transmitted, used or the like. The injected signals can be any signals including a series of pulses, a swept frequency signal or a random signal. The circuit can also include an inhibit circuit coupled to the output terminal of the phase lock loop which normally inhibits an output from the output terminal of the phase lock loop and is responsive to a substantial match of the signal generated by the signal generator and the signal injected into the phase lock loop to disinhibit the inhibit circuit.