The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 1998

Filed:

Apr. 26, 1996
Applicant:
Inventors:

David Michael Pietruszynski, Austin, TX (US);

James Dub Austin, Austin, TX (US);

Brian Kirkland, Austin, TX (US);

Assignee:

Crystal Semiconductor, Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
327379 ; 327109 ; 327309 ; 327333 ;
Abstract

An output driver is provided for operating in a primary power supply environment to drive an output system that can have voltages associated therewith that are higher than the primary power supply level. The driver includes a pull-down N-channel (34) and a pull-up P-channel transistor (44). An output node (40) is driven by the transistor (34) and (44). An N-channel protection device (38) is disposed between node (40) and transistor (34) and an N-channel transistor (48) is disposed between node (40) and transistor (44). Transistor (38) has the gate thereof biased to the primary supply voltage level and the transistor (48) has the gate thereof biased to a voltage slightly above the primary supply voltage level. This configuration allows a common control signal varying up to the primary power supply level utilized to drive both transistors (34) and (44) and also to remove the requirement that any of the wells associated with the driver transistors be biased to a voltage above the primary supply voltage level, to prevent current being conducted to the primary supply from the output node during a high voltage condition or for the voltage of any of the transistors to exceed a voltage slightly above that of the primary voltage supply level.


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