The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 12, 1998

Filed:

Jan. 02, 1997
Applicant:
Inventors:

David M Heminger, Mesa, AZ (US);

Joseph H Slaughter, Chandler, AZ (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257173 ; 257402 ; 257403 ; 257360 ;
Abstract

A current limiter (15) is formed between a silicon substrate (10) and a source region (17) by a channel implant region (20). The channel implant region (20) is not modulated by a gate structure so the maximum voltage that can flow between the silicon substrate (10) and the source region (17) is determined by the doping profile of the ever-present channel implant region (20). A pinch-off structure (12) is used to form a depletion region which can support a large voltage potential between the silicon substrate (10) and the source region (17). In an alternate embodiment, a bipolar device is formed such that a limited current flow can be directed into a base region (32) which is used to modulate a current flow between silicon substrate (30) and an emitter region (38). Using the current limiters (15,35) it is possible to form an AC current limiter (50) that will limit the current flow regardless of the polarity of the voltage placed across two terminals (51,52).


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