The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 1998

Filed:

Apr. 26, 1996
Applicant:
Inventor:

Yukio Kobayashi, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ;
U.S. Cl.
CPC ...
39518318 ; 395456 ; 395468 ; 371 212 ;
Abstract

A cache memory testing method is employed to test a cache memory control mechanism which controls data coherency between cache memories or between a main storage unit and a cache memory in a system including N processors each having a cache memory and coupled to the main storage unit, where the processors are access sources and N is an integer greater than one. The cache memory testing method includes the steps of (a) dividing a control unit depending on N, and allocating access regions within the cache memories at positions which are mutually different and are peculiar to each of the N processors in the divided portions of the control unit, where the control unit is a mechanical minimum unit of the data coherency control, and (b) testing the cache memory control mechanism based on read data by writing data to and reading data from only the peculiar access regions within the same control unit by each of the N processors.


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