Fast scan gra cell circuit

Abstract

A GRA cell used in logic for digital systems has a master/slave latch circuit which has a L1 master latch circuit and an L2 slave latch circuit. The L1 master latch circuit having a first cross-coupled portion and a complementary write circuit coupled to the slave latch and having scan-in port coupled to pass a scan-in signal to an L1 pass gate NFET transistor. An A.sub.-- Clock terminal port is connected to the L1 pass gate NFET transistor. The L2 slave latch's input is an output from the L1 master latch circuit. This L2 slave latch includes a second cross-coupled portion and a complementary write circuit. The L2 slave latch circuit is coupled to receive a signal resulting from the scan-in signal via said L1 latch circuit and an L2 pass gate NFET transistor for testing of said master/slave latch circuit. A B.sub.-- Clock terminal is connected to the L2 pass gate NFET transistor. This allows testing to be used with the single NFET pass gate transistors for each latch. In order to reduce soft errors and required voltage and increase scan speed both L1 and L2 latch clock inputs during a scan function are connected respectively to their respective NFET pass gate transistors and to the source of their respective NFET feedback NFET transistor's circuit's source. During a test scan the pass gate and source of a feedback NFET transistor are coupled to their respective input clocks. The latch signal of each of said L1 master latch circuit and said L2 slave latch circuit receive their respective A.sub.-- Clock and B.sub.-- Clock signals, and turning each feedback NFET transistor fully on during one clock cycle and fully off during another portion of a clock cycle allows a very fast scan to be used during testing and diagnostic inspection of the circuit cell.