Asynchronous transfer mode cell processing system with load multiple

Abstract

Methods and apparatus for processing cells in an asynchronous transfer mode (ATM) communication system. An ATM cell processor includes a load multiple instruction which provides a burst transfer of a data block from an external control memory, and allows the result of a subsequent operation on a loaded value to be automatically written back to the control memory location from which it was previously read. The instruction may specify the address in the control memory of a data block to be retrieved, a destination register in a CPU register file into which the first retrieved halfword of a data block will be loaded, and a total number of halfwords to be retrieved. The instruction includes a link field option which directs the storage of information linking the processor registers which receive the retrieved halfwords to the control memory locations from which the halfwords were read. An automatic memory update feature may be provided in an arithmetic logic unit (ALU) instruction which operates on one or more of the processor registers receiving the halfwords retrieved by the instruction, such that the result of the corresponding ALU operation will be automatically written back to the control memory location or locations which supplied one or more of the operands.