Address buffer for high-speed address inputting

Abstract

An address buffer for a semiconductor memory device having an address input buffer and an address predecoder incorporated together so as to be driven in a single channel, capable of reducing an address predecoding time by a logic combination of outputs of address input buffer, for high speed of operation of a memory device. The address buffer is provided with one or more address input means connected between a power supply voltage and a ground voltage, for amplifying a given number of addresses received from an external device to thereby provide a stable level of outputs in response to an address input enable signal, a delay circuit having inputs connected with the outputs of said address input means, for converting the outputs of said address input means into a stable logic level and delaying the outputs by a given time interval for a delivery in conformity with the addressing time, an address predecoder connected with the outputs of said delay circuit, for providing a decoded address according to a predetermined logic combination of the outputs of said delay circuit, a transmission latch circuit coupled to said address predecoder, for transmitting and latching the decoded address from said address predecoder in accordance with an address latch signal, and an output driver coupled to said transmission latch circuit, for driving the decoded address output from said transmission latch circuit in a stable level for a delivery to a memory cell.