Self repairing integrated circuit memory devices and methods

Abstract

Self repairing integrated circuit memory devices include the plurality of normal memory cells, plurality of spare memory cells and a plurality of spare substituting circuits. A spare substituting circuit is responsive to a defective normal memory cell address which is programmed therein, to substitute at least one spare memory cell for at least one defective normal memory cell which is located at the defective normal memory cell address which is programmed therein. A sequential spare substituting circuit selector is connected to the spare substituting circuits and is responsive to a defect indication signal, to sequentially select a respective one of the spare circuits for programming with sequential ones of the defective normal memory cell addresses. An alarm signal is generated if all of the spare substituting circuits have been used. If a defect is present in at least two normal memory cells in different rows and the same column, a spare column is substituted rather than two spare rows. Also, if all rows substituting circuits have been programmed spare column substituting circuits are used. Defective addresses are programmed using electrically programmable fuses preferably polycrystalline silicon elongated fuses.