High speed method and apparatus for detecting assertion of multiple

Abstract

A multiple match detection circuit including an array of N and P-channel pull-up and pull-down devices receiving a corresponding array of hit line signals for developing complementary bit line signals, which are provided to the respective inputs of a differential comparator. Respective buffers drive the bit line signals to a maximum voltage differential in normal mode. For each hit line asserted, the pull-up and pull-down devices modify the voltage of the corresponding bit line voltage between the bit lines by an incremental amount, thereby decreasing the differential. Any single hit line does not cause enough of a voltage change to reverse the polarity of the differential voltage between the bit lines. However, if more than one hit line is asserted, the combined incremental change of voltage due to activation of two or more pull-up and pull-down devices is greater than the maximum voltage differential between the bit line signals asserted by the buffers, causing the bit line differential voltage to reverse polarity. The differential comparator detects the reversal of polarity of the bit line differential voltage and asserts an error signal. The multiple detection circuit further includes a transmission gate, which selectively equalizes charge on the bit lines, and isolation devices, which provide level shifting, prior to detection by the differential amplifier to thereby increase the speed of detection.