The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 1998

Filed:

Jan. 05, 1996
Applicant:
Inventors:

Michael Patrick Beakes, Yorktown Heights, NY (US);

Barbara Alane Chappell, Portland, OR (US);

Terry Ivan Chappell, Portland, OR (US);

Bruce Martin Fleischer, Mt. Kisco, NY (US);

Rudolf Adriaan Haring, Cortlandt Manor, NY (US);

Talal Kamel Jaber, Autin, TX (US);

Edward Seewann, Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
326 93 ; 326 16 ; 326 21 ; 326 40 ; 371 225 ;
Abstract

A pulsed logic circuit test methodology and circuitry therefor are disclosed. The methodology and circuitry allow the inhibiting of reset pulses, the ability to force resets and the ability to test the circuit in a pseudo-static mode of operation.


Find Patent Forward Citations

Beakes, Michael. (1998). Methodology to test pulsed logic circuits in pseudo-static mode (U.S. Patent No. 5748012). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5748012

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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