The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 05, 1998

Filed:

Jun. 25, 1996
Applicant:
Inventors:

Kenichi Kuroda, Tachikawa, JP;

Kazuyoshi Shiba, Kodaira, JP;

Akinori Matsuo, Higashiyamato, JP;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257321 ; 257316 ; 36518501 ;
Abstract

A semiconductor substrate of a first conductivity type has formed on its main surface a floating gate through a first gate insulating film and has further formed over the floating gate a control gate through a second gate insulating film. In one of a paired source and drain and across which there is provided the floating gate insulately above the main surface of the substrate, a semiconductor region of second conductivity type having a lower impurity concentration than that of the paired source and drain is formed in a portion of the substrate overlapping the floating gate. A nonvolatile memory device thus constructed has its writing operation carried out by extracting electrons from the floating gate to the other of the paired source and drain having a semiconductor region of the second conductivity type, having a higher impurity concentration, by an F-N tunneling of electrons flowing through the first gate insulating film and its erasing operation carried out by injecting from the paired source and drain or the semiconductor substrate into the floating gate by the F-N tunneling of electrons flowing through the first gate insulating film. Data lines or source lines can be shared between memory cells adjacent to each other in a word line direction so that the memory cells can be substantially small-sized. The writing operation and the erasing operation can be carried out by the tunnel current so that the corresponding necessary high voltages can be generated by the internal circuits.


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