The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 1998
Filed:
Jul. 24, 1996
Robert M Young, Pittsburgh, PA (US);
Carl B Freidhoff, Murrysville, PA (US);
Timothy T Braggins, Pittsburgh, PA (US);
Thomas V Congedo, Pittsburgh, PA (US);
Northrop Grumman Corporation, Los Angeles, CA (US);
Abstract
A gas ionizer is provided for use in a solid state mass spectrograph for analyzing a sample of gas. The gas ionizer is located in a cavity provided in a semiconductor substrate which includes an inlet for introducing the gas to be analyzed. The gas ionizer ionizes the sample of gas drawn into the cavity through the inlet to generate an ionized sample gas. The gas ionizer generates energetic particles or photons which bombard the gas to be sampled to produce ionized gas. The energetic particles or photons can be generated by reverse-bias p-n junctions, radioactive isotopes, electron discharges, point emitters, and thermionic electron emitters. A layer of cesium chloride or cesium iodide having a low work function is formed on top of the reverse-bias p-n junction gas ionizer to increase current emitted per junction area and so that the gas ionizer can be exposed to atmospheric oxygen during storage and can operate in reduced atmosphere with no additional treatments. The cesium chloride layer and the cesium iodide layer do not readily electromigrate. A fabrication process of the mass spectrograph includes using plural masks to ensure proper exposure of resist on both flat and wall surfaces of the semiconductor surface having severe topography.