Phase-shifted embedded ram apparatus and method

Abstract

The present invention is an embedded random access memory device especially adapted for use with digital processors having a pipelined data architecture. In accordance with one embodiment of the present invention a write access cycle performed at a memory location within the memory device is phase shifted by one phase of a clock cycle relative an access cycle of a read operation. This is advantageous in that the integrity of data which traditionally would have been presented late in the write access cycle can still be maintained, since the entire write cycle is now shifted one phase later. A precharge signal which follows the write access is correspondingly shifted by one phase of a clock cycle. A wait state is inserted between the write access cycle and a read access cycle which directly follows in the same memory bank of the memory device. The wait state eliminates conflicts between the access cycle and the precharge cycle.