The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 28, 1998
Filed:
Apr. 06, 1995
Katsuaki Saito, Hitachi, JP;
Michio Ohue, Hitachi, JP;
Takuya Fukuda, Hitachi, JP;
JaiHo Choi, Hitachi, JP;
Yukinobu Miyamoto, Hitachi, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
A semiconductor integrated circuit apparatus according to the present invention has a capacitor formed in such a manner that a ferroelectric thin film is formed after a MOS transistor has been formed on a substrate thereof, a ferroelectric thin film made of, for example, PbZrTiO.sub.3 or SrTiO.sub.3 or the like is formed into a columnar shape to form electrodes positioned in direct contact with the side wall portions of said columnar ferroelectric thin film and the top portion is removed. As a result, a fact that an oxide of each electrode, which deteriorates the relative permittivity, is formed on the interface between the electrode and the ferroelectric material is prevented, and a large capacity can be realized with respect to the area of the substrate because the ferroelectric thin film is formed into the columnar and elongated shape, resulting in that the capacitance of the capacitor is not reduced in which the electrodes and the oxide dielectric material having a high permittivity are, in series, connected to each other. The capacitor is formed into a DRAM or an FRAM memory cell so as to realize a semiconductor memory revealing a high degree of integration and a high processing speed.