Computer system with programmable driver output's strengths responsive

Abstract

A computer system is presented which includes an output driver circuit with a drive strength that varies depending upon the speed of a peripheral device being accessed, the frequency of a system clock signal, and/or the system configuration. Reducing drive strength when a slow peripheral device is being accessed, the frequency of the system clock signal is reduced, or bus loading is low reduces the occurrence of large switching transients and accompanying ground bounce, power supply droop, and radiated EMI. A power management unit produces a clock frequency control signal which controls the frequency of the system clock. In one embodiment, the output driver circuit includes an address storage unit, an address comparator unit, a bus loading storage unit, a control unit, and one or more adjustable drive circuits having an output terminal coupled to a signal line of a peripheral bus. The address storage unit stores address range information associated with one or more peripheral devices coupled to the peripheral bus. The address comparator unit produces an address match signal if an address signal is within a range of addresses identified by address range information stored in the address storage unit. The bus loading unit stores peripheral bus loading information. The control unit produces one or more control signal dependent upon the address match signal, the clock frequency control signal, and/or bus loading information. Each adjustable drive circuit drives the output terminal with a drive strength determined by the one or more control signals.