Error-handling circuit and method for memory address alignment double

Abstract

In an .chi.86-compatible processor capable of operating in a protected mode of operation in which privilege levels are assigned to tasks executing therein, an application task being assigned a lowest privilege level and executable in the processor to cause the processor to calculate addresses corresponding to specific locations in a computer memory associated with the processor, the addresses to be in alignment with respect to the computer memory prior to the processor issuing the addresses, a circuit for, and method of, handling sequential alignment faults and a computer system embodying the same. The circuit includes: (1) an alignment detection circuit to detect an alignment fault and generate an alignment check exception in response thereto and (2) an alignment fault-handling routine associated with the processor, executable in response to generation of the alignment check exception, operable to detect a sequential alignment fault and generate a double fault exception in response thereto, the alignment fault-handling routine thereby allowing the processor to avoid a third sequential alignment fault.