Power reduction method and apparatus for phase-locked loop based clocks

Abstract

A method and apparatus for reducing power associated with acquiring phase-lock between a reference clock signal and an internal clock signal after each exit from a quiescent state by a data processing system. A phase-locked loop (PLL) phase-locks the internal clock signal to the reference clock signal. A set of clock drivers receive an oscillator signal from the PLL and generate a plurality of multi-phase internal clock signals in response thereto. The clock state machine receives a first control signal from the PLL, indicating that the phase-locked loop is re-acquiring phase-lock as a result of the data processing system leaving a quiescent state. The clock state machine suppresses a set of clock state signals to prevent the clock drivers from changing state during the period of time when the phase-locked loop is re-acquiring phase-lock. The invention reduces power consumption associated with acquiring phase-lock by eliminating the power resulting from toggling the clock drivers during each exit from the quiescent state by the data processing system.