The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 1998

Filed:

Apr. 09, 1996
Applicant:
Inventors:

Robert J Fronen, Nijmegen, NL;

Johannes P De Vries, Eindhoven, NL;

Assignee:

U.S. Philips Corporation, New York, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
327382 ; 327108 ; 327333 ; 327380 ; 327389 ; 327390 ; 327427 ; 327434 ;
Abstract

A level-shifting circuit (LS.sub.A) including a series arrangement of a load resistor (R.sub.A), a main current path of an input transistor and a bipolar series transistor (T3.sub.A) arranged as a current source and having a parasitic transistor with a small current gain factor, which is obtained, for example, by wholly surrounding the comparatively weakly doped collector region with a comparatively heavily doped material of the same conductivity type as the collector region. When the input transistor (T1.sub.A) is not conductive a large amount of charge accumulates in the series transistor (T3.sub.A), which is then in saturation. When the input transistor (T1.sub.A) is turned on the accumulated charge causes an overshoot in the current (I.sub.A) through the level-shifter which overshoot compensates for the slow response as a result of the parasitic capacitance (PC.sub.A) at the node (N.sub.A).


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