Series-structured read-only memory having word lines arranged

Abstract

A semiconductor memory device which has a reduced current consumption. A memory block includes a pair of memory cell columns each of which includes a plurality of memory cells connected in series, the memory cell columns being connected in series in a column direction along which the memory cells are arranged, a position of each of the memory cells being indicated by address data comprising first address data and second address data. Each of a plurality of word lines is connected to a corresponding one of the memory cells included in the memory block on a one to one basis. A memory cell column selection decoder selects one of the memory cell columns based on the first address data. A word line selection decoder selects one of the word lines based on the second address data and a control signal which is logically equivalent to the first address data. Additional memory blocks may be arranged in a row direction perpendicular to the column direction. Each of the bit lines may be connected to a data line via a switch unit so that one of the bit lines is precharged via the data line when the switch unit is conductive.