The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 14, 1998
Filed:
May. 31, 1996
David R Smentek, Columbia, MD (US);
Craig A Heikes, Fort Collins, CO (US);
Robert H Miller, Jr, Loveland, CO (US);
Hewlett-Packard Company, Palo Alto, CA (US);
Abstract
An apparatus and method are disclosed for regulating power consumption in a digital system of the kind including at least one triggerable functional block that consumes more power when triggered than when not triggered. In an embodiment for use with a digital system that includes a pipeline of such triggerable functional blocks, a state machine sequentially applies trigger pulses to each of the functional blocks in the pipeline whenever the output of an OR gate is asserted. It does so by generating a series of enable signals that are used to gate a clock signal to the trigger inputs of the functional blocks. The state machine includes a series of storage devices having outputs. Outputs of the storage devices are used to provide the enable signals. The inputs of the OR gate are coupled to a start signal that indicates when the functional blocks should be triggered to process data, and also to a dummy start signal that indicates when the functional blocks should be triggered to maintain power consumption. Outputs from the storage devices are also used to indicate the number of times the pipeline has been triggered during a recent number of clock cycles. A programmable register is used to store a data value corresponding to the minimum desired level of power consumption for the pipelined functional blocks. The dummy start signal is generated by combinational logic whose inputs include the outputs of the storage devices and the data value. Because the minimum desired level of power consumption may be programmed by the user, thermal characterization and balancing of step load with average power are facilitated.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile