Voltage regulator with high gain cascode current mirror

Abstract

The present invention provides a voltage regulator especially adaptable for use with a field-programmable gate array (FPGA). The voltage regulator of the present invention rapidly generates an operating voltage for the core or nucleus logic elements upon application of external power while preventing degradation of the fuses. The core or regulated voltage of a FPGA can be set to a level that provides maximum performance with minimum power consumption or, alternatively, permits propagation delays and switching rates to be adjusted so as to compensate for die to die variation. Since it is common for electrical parameters of FPGA manufactured in different wafer fabrication facilities to vary, the voltage regulator is configurable as a true voltage regulator or, alternatively, as a pseudo-voltage regulator. The voltage regulator comprises an operational transconductance amplifier with a single gain stage followed by an NMOS source follower. The amplifier is frequency compensated at the high impedance output of the amplifier by a capacitor coupled to V.sub.SS. The voltage regulator further includes circuitry to improve performance during the power-up sequence and to a novel cascode connection that minimizes the external voltage that must be applied to the regulator. The amplifier contains a novel cascode connection on its inputs.