The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 1998

Filed:

Jun. 18, 1996
Applicant:
Inventors:

Mitsuhiro Saitou, Obu, JP;

Kouji Numazaki, Nukata-gun, JP;

Hiroyuki Ban, Hazu-gun, JP;

Assignee:

Nippondenso Co., Ltd., Kariya, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257 48 ; 257207 ; 257210 ; 257211 ; 257620 ; 437-8 ;
Abstract

A semiconductor wafer, having a relatively wide power supply line and ground line, and which can also prevent short-circuiting between these lines. Multiple integrated circuit formation regions, whereon integrated circuits have been formed, are disposed on a semiconductor wafer. A silicon oxide film is formed on a silicon substrate, and a ground line conductor is formed on the silicon oxide film. This ground line conductor is extended over scribe lines. A layer insulation film composed of silicon oxide film is deposited on the silicon oxide film with the ground line conductor interposed therebetween, and a power supply line conductor is formed on the layer insulation film to overlap the ground line conductor. The power supply line conductor is extended over scribe lines. In the integrated circuit formation regions, a power supply pad and the power supply line conductor are electrically connected. A ground pad and the ground line conductor are also electrically connected.


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