Cache memory which selects one of several blocks to update by digitally

Abstract

A cache memory includes: a plurality of tag memory blocks, each of which stores multiple compare addresses; a first bus which sends a low order address to all of the tag memory blocks; a respective output from each tag memory block on which a compare address is read in response to the low order address; a second bus which carries a high order address; and, a comparator circuit which generates a miss signal when the compare address on the output from every tag memory block miscompares with the high order address. Each tag memory block further stores respective control bits with each compare address; and each tag memory block responds to the low order address by reading the compare address and the respective control bits, in parallel, on its respective output. A digital logic circuit is coupled to the outputs from all of the tag memory blocks; and this digital logic circuit selects one of the tag memory blocks to write, when the miss signal occurs, by digitally combining the control bits that are read by the low order address from all of the tag memory blocks.