Method and apparatus for data path circuit layout design and memory

Abstract

The present invention provides a data path circuit layout design method capable of generating a mask layout which satisfies timing specifications and given contour conditions, and which is reduced in circuit area. There are prepared function macros in each of which there is defined an expansion, according to the parameters, to a circuit comprising a plurality of schematic leaf cells. For a data path circuit of which function blocks are described by function macros, the placement of the function blocks is optimized by a function macro placement process. By a function macro expansion process, the function macros describing the function blocks are expanded and connection information on the schematic leaf cell level are prepared. By a detail placement and routing process, the schematic leaf cells are replaced with the corresponding layout leaf cells and the layout leaf cells are wired to one another, thereby to generate a mask layout of the data path circuit.