Fpga with parallel and serial user interfaces

Abstract

A configuration structure for a field programmable gate array (FPGA) allows a user to reconfigure or partly reconfigure the FPGA from within the FPGA, allows an addressable configuration memory to be addressed in parallel through a set of address and data or through a serial interface. Signals such as chip-enable and other control signals can be modified by user logic so that data loaded through a serial interface pin is entered into an addressed portion of configuration memory. The configuration memory programs not only the internal circuitry accessed by the user but also a programmable switch for directing signals between external pins, configuration memory control lines, and a serial data interface. Providing both parallel and serial interfaces allows a programmable switch which is initially configured to connect its related pad or pads to configuration control lines such as a chip enable line or a serial data input line to later be configured to connect an internally generated signal or signals to the line or lines and thus override any external signal which would have been connected to that line or lines.