Apparatus for databus fault isolation

Abstract

Apparatus for replacing conventional fault isolation resistors includes a terminal coupled to one winding of a transformer whose other winding is coupled across the two-line databus. Enhancement-mode-field-effect transistors have their source and drain electrodes each coupled between one end of the other winding and one of the databus lines and their control electrodes coupled at spaced intervals along the other winding. The winding voltage is zero when a terminal is not transmitting, turning off the field-effect transistors, presenting an open circuit. The parasitic body diodes of the transistors are connected in series and are poled to oppose each other to prevent conduction of signals from the databus. Thus, signals on the databus are not loaded by the terminal's output impedance. When winding voltage exceeds a threshold, one transistor conducts, providing substantially a short-circuit. The parasitic body diode of the remaining transistor also conducts. When the winding voltage reverses, the conductive states of the transistors are reversed. When the databus is coupled to a receiver by a separate transformer, fault isolation resistors protect the receiver path. When the transmitter and receiver use a common path between the databus and the terminal, higher resistance value fault isolation resistors are placed in parallel with each field-effect transistor, reducing reflections in the databus in the event of a fault. The transistors are preferably enhancement-mode MOSEFTs of either the N-channel or P-channel type; although bipolar transistors or insulated gate bipolar transistors may be employed.