The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 1998
Filed:
Oct. 09, 1996
Robert Andrew Kertis, Rochester, MN (US);
Joe Martin Poss, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A high speed differential analog to digital converter (ADC) is provided. The high speed differential ADC includes a driver section, a comparator section and a decoder section. The driver section includes a pair of series connected resistor ladders. A positive phase and negative phase emitter follower transistor pair is connected to the pair of series connected resistor ladders. The positive phase and negative phase emitter follower transistor has a collector connected to a supply voltage and has an emitter coupled to a respective one of the pair of series connected resistor ladders. A respective positive phase and negative phase AC current source drives the base of the respective positive phase and negative phase emitter follower transistor. A reference DC current source is coupled to the base of the positive phase and negative phase emitter follower transistors for determining a range of the ADC. A current source transistor pair biases the emitter follower transistor pair. A first transistor of the current source transistor pair supplies current to the positive phase emitter follower transistor and a second transistor of the current source transistor pair supplies current to the negative phase emitter follower transistor. The first transistor has a control node capacitively coupled to the emitter of the negative phase emitter follower transistor and the second transistor having a control node capacitively coupled to the emitter of the positive phase emitter follower transistor.