The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 1998
Filed:
Mar. 04, 1997
Ming-Chien Chang, Hsinchu, TW;
Wuu-Larng Laih, Chiai Hsien, TW;
Vanguard International Semiconductor, Corporation, Hsinchu, TW;
Abstract
A method for manufacturing input/output port devices of a semiconductor circuit having low body effect, suitable for use on a semiconductor substrate on which a plurality of pull-up device regions and pull-down device regions are formed. First, when executing a channel implantation, an anti-punchthrough implantation, and a threshold adjustment implantation, a mask which masks PMOS devices in the CMOS process is used to mask pull-up device regions on a semiconductor substrate. Furthermore, when executing a cell implantation, a mask which masks the outside regions of memory cells is used to mask pull-down device regions. In the invention, the body effect of pull-up devices on the input/output port is reduced without using any extra mask and under the original process, thereby lowering the threshold voltage and reducing the output voltage drop.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile