The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 31, 1998
Filed:
Jun. 02, 1995
Akiko Satoh, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
An interactive logic simulation system includes a setting unit for setting at least one display format for logic simulation result information in the form of a window defined by an arbitrary display range by interacting with a user through a display screen; a first management table for managing the display mode of a free-format display format set by the setting unit; a second management table for managing the display mode of a stream display format as a time series display format of the logic simulation result information; a third management table for managing time series data of signal values for each signal terminal constituting the logic simulation result information; and a result display control unit for specifying the logic simulation result information by using management data from the first, second and third management tables, and for displaying the logic simulation result information so specified on the display screen. The system simultaneously displays the logic simulation result information in the free-format display format at a designated time and the logic simulation result information in the stream display format at the designated signal terminal, in the window set on the display screen. Such a construction makes it possible for a user to efficiently conduct execution and analysis of simulation without particularly considering the troublesome procedures and the operations of the logic simulation. When the simulation procedure of the next stage is considered, a high operation factor can be provided by reducing the interruption to the consideration.