The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 31, 1998
Filed:
Aug. 09, 1995
Charles E Moore, Loveland, CO (US);
Richard A Baumgartner, Palo Alto, CA (US);
Travis N Blalock, Santa Clara, CA (US);
Thomas M Walley, Loveland, CO (US);
Robert A Zimmer, Loveland, CO (US);
Rajeev Badyal, Ft. Collins, CO (US);
Li Ching Tsai, Ft. Collins, CO (US);
Larry S Metz, Ft. Collins, CO (US);
Sui-Hing Leung, Cupertino, CA (US);
James S Ignowski, Ft. Collins, CO (US);
Kenneth R Stafford, Ft. Collins, CO (US);
Ran-Fun Chiu, Los Altos, CA (US);
Richard A Baugh, Palo Alto, CA (US);
Hewlett-Packard Co., Palo Alto, CA (US);
Abstract
An analog, fully integrated, partial response maximum likelihood (PRML) read channel utilizing a high-performance analog delay line, an analog adaptive equalizer and an analog Viterbi detector is provided, resulting in saved space, performance gains, and lower power consumption. For signal detection and reconstruction used in read operations, the partial response maximum likelihood (PRML) read channel includes a variable gain amplifier coupled to a lowpass filter for input to an adaptive analog equalizer. The adaptive analog equalizer comprises an analog delay line and an analog feedforward equalizer (FFE). An analog Viterbi detector employs maximum-likelihood sequence estimation (MLSE) techniques to performs the signal detection function. A decoder/descrambler produces a final reconstructed signal. The analog implementation of a partial response maximum likelihood (PRML) read channel also includes a scrambler/encoder coupled to a write precompensation circuit for output to a separate write head.