The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 31, 1998
Filed:
Nov. 12, 1996
Gregg Dierke, San Jose, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A testing apparatus is integrally formed on a microelectronic integrated circuit chip for testing a plurality of memories including parallel outputs having a total of a first number of bits. The apparatus includes an input unit for writing test data into the memories, a parallel output bus having a second number of bits which is smaller than the first number of bits, and an output unit for selectively connecting outputs of the memories to the output bus such that a total number of bits of the selected outputs is not greater than the second number of bits. The outputs of the memories are connected to the output unit in groups, and the output unit is configured to selectively connect the groups of outputs to the output bus in response to respective control signals to read test data out of the memories. Data is applied from the memories to the output unit in bytes. For memories that have parallel outputs wider than one byte of data, multiplexers are provided for successively applying the data from the memories to the output unit one byte at a time. Output data is true data, not encrypted to reduce bits and, thusly, observability.