Method and apparatus for superimposing self-clocking multifunctional

Abstract

A communication system for allowing a master to send commands to one or more slave devices across a normally static digital signal line of a bus. The master includes command logic for asserting a sequence of digital pulses according to a predetermined protocol with inherent timing to clock each data bit into a slave device. The master transmits several data bits to form each command, where each data bit is combined with clocking pulses to implement the self-clocking scheme. In particular, an initial data pulse incorporates a data bit to initiate a data phase. Each slave device includes a state machine which detects the data pulse and enables a sample and hold or latch circuit to capture the data bit. Then a clock pulse followed by a reset pulse is sent to clock the data into the slave device and reset the state machine. The slave also includes shift register logic to hold a command bit and address bits for each command. Decode logic compares the address with a predetermined code, where if a match occurs, the command bit is executed. Two masters may be included for sending superimposed pulses to two types of slave devices. One type of slave device includes pulse detection circuitry for detecting positive going pulses on the static digital line, and the other type detects negative going pulses.