Data memory and processor bus

Abstract

A data processing system has a CPU linked via a unidirectional read bus and a unidirectional write and address bus to a data memory (e.g., cache, RAM, or disk), in the form of a cache memory. Since the read bus and the write and address bus are only driven in one direction, lost time through reversing the direction of signals travel along a bus is avoided. Read-data words and instruction-data words are transferred from the cache memory to a core of the CPU via the read bus. Instruction-address, read-address, write-address, and write-data words are time division multiplexed on the write and address bus to pass from the core to the cache memory. The system supports burst mode transfer thereby reducing the number of addresses that need to be transferred on the write and address bus thereby releasing bandwidth on this bus for use by write-data words.