Semiconductor memory device having a burn-in control circuit and burn-in

Abstract

A burn-in test circuit for a semiconductor memory device tests for defective memory cells. The test circuit applies a test signal that turns 'off' transistors in a precharge circuit and applies a select signal to memory cells at predetermined intervals. The select signal and test signal are delayed for different time intervals depending on whether the memory device is transitioning from a normal operating mode to a test mode or from the test mode to the normal operating mode. The selective delay prevents overcurrent conditions from occurring during the mode transitions.