The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 24, 1998
Filed:
Jul. 22, 1996
Applicant:
Inventor:
Timothy D Dorney, Houston, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365200 ; 365210 ; 3652301 ;
Abstract
A semiconductor memory device (10) includes a plurality of row address inputs (RA0-RA8), and a plurality of column address input (CA0-CA8) lines. A plurality of main memory subarrays (122) include a plurality of memory cells (122). A plurality of redundant memory arrays are associated with the main memory arrays. Column redundancy circuitry (68) receives column addresses (CA3-CA7) for determining if a match occurs between the received column addresses and the stored redundant column information.
Dorney, Timothy. (1998). Method and system for reduced column redundancy using a dual column (U.S. Patent No. 5732030). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5732030
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile