Method and circuit for testing memory cells in semiconductor memory

Abstract

A test control circuit and method of testing a memory cell in a semiconductor memory device. The test control circuit includes a memory cell array having a plurality of normal memory cells to store data on a semiconductor substrate and a plurality of redundancy memory cells to substitute for defective normal memory cells. Row and column redundancy fuse boxes include fuse elements to be electrically fused to enable row and column redundancy decoders for selecting rows and columns of the redundancy memory cells. A redundancy cell test signal generator generates, in response to a test signal applied to an extra line in the address bus, a master clock for testing the redundancy memory cell under the same mode as a test mode of the normal memory cell. A test controller provides an enable signal for selecting the redundancy memory cells of a memory array in response to logic levels of the master clock and an address signal applied during the redundancy memory cell test.