Combined program and data nonvolatile memory with concurrent

Abstract

A nonvolatile memory device includes two floating-gate-type memory arrays, e.g. a flash memory intended to be used as a relatively permanent program memory and an E.sup.2 PROM intended to be used as a more frequently updated data memory. A single set of address lines and a single set of data lines are used for both read and write operations for both memory arrays. Address decoding means for accessing an addressed location of a selected memory array includes separate column decoders and data latches for each array, but also includes a shared row decoder common to both arrays. Row address latching circuitry associated with at least the data memory holds a decoded row address for that memory array during a write operation so as to free the shared row decoder for use on one or more concurrent read operations for the other memory array, e.g. the program memory. Data I/O buffer circuitry and sense amplifiers are also shared by both arrays. Control logic, responsive to input control signals selecting one of the memory arrays and selecting a read or write operation, controls the various elements of the device, including address and data latches and select/driver circuitry, to carry out the desired operations.