The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 24, 1998
Filed:
Dec. 04, 1995
Issam S Abu-Khater, Lake Oswego, OR (US);
A Bellaouar, Waterloo, CA;
Mohamed I Elmasry, Waterloo, CA;
The University of Waterloo, Ontario, CA;
Abstract
A low power high performance adder using a conditional sum adder (CSA) architecture and complementary pass logic (CPL) implementation. The adder comprises a plurality of blocks, each block including a conditional sum cell and an output multiplexer. Each block except the first, also comprises a block of 2:1 multiplexers intermediate the conditional sum cell and the output multiplexer. The adder according to the present invention operates with lower power consumption and at greater speed than prior art adder architectures.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile