Half symbol delay calibration for phase window centering

Abstract

The present invention provides a method and apparatus for half symbol delay calibration for phase window centering. To perform calibration of phase window centering, a carefully designed input signal is applied to the data signal input of a phase detector and a corresponding gating signal is applied to each of two D flip-flops. A calibration circuit produces the gating signal to enable the D flip-flops and the complement of the gating signal to temporarily prevent disturbance of a charge pump. In the preferred embodiment of the present invention, the calibration circuit provides a divide-by-4 clock function. The carefully designed input signal used for calibration includes on-time pulses and time-shifted pulses. The on-time pulses have rising edges that rise with the rising edges of the VCO clock signal. The time-shifted pulses follow the on-time pulses by 2.5 clock cycles of the VCO clock signal. If the half symbol delay is optimized, the phase detector will be equally likely to produce a pump up or a pump down signal. If the time-shifted pulses occur early or late relative to the rising edges of the VCO clock signal, then there will be more pump up or more pump down signals respectively. This information is used to calibrate the half symbol delay.