The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 1998
Filed:
Mar. 11, 1996
Applicant:
Inventors:
Glen J Zoerner, Austin, TX (US);
Danny H Nguyen, Austin, TX (US);
Assignee:
Motorola Inc., Schaumburg, IL (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R / ;
U.S. Cl.
CPC ...
324765 ; 324763 ;
Abstract
A method for testing a phase locked loop (103) within an integrated circuit (100) is performed by utilizing an on-chip timer module (100) as a frequency counter (121) for counting the number of clock pulses outputted from the phase locked loop circuit (103) over a selected time period. The test is performed by an external testing device (111) having access to the address/data bus (110) coupled to both the phase locked loop circuit (103) and the timer module (109).
Zoerner, Glen. (1998). System and method for testing a phase locked loop in an integrated (U.S. Patent No. 5729151). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5729151
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile