Semiconductor memory device having a redundant configuration

Abstract

A semiconductor memory device includes a plurality of memory cells, a plurality of address detecting circuits capable of registering a defective address indicating a defective memory cell out of the plurality of memory cells for detecting whether an external address matches the defective address or not and each corresponding to 1 bit of the external address or complementary 1 bit thereof, and first and second terminals. Each of the address detecting circuits includes first and second capacitors each having a floating electrode formed of the same layer as a cell plate electrode of a memory cell, a fixed electrode formed of the same layer as a storage node electrode of the memory cell, and a dielectric layer formed of the same layer as a dielectric layer of the memory cell and formed between the floating electrode and the fixed electrode. If 2.times.Vcc is applied to the first terminal and 2.times.Vcc+.delta. is applied to the second terminal, charges are charged in the first and the second capacitors. If ultraviolet rays are directed to the second capacitor, charges are left in respective floating electrodes of the first and the second capacitors, whereby the defective address can be registered in a non-volatile manner. Accordingly, the semiconductor memory device can be manufactured without increase in the number of manufacturing steps, and can replace a defective memory cell with a spare memory cell.