Hierarchical encoder including timing and data detection devices for a

Abstract

A encoder has a prefetch circuit or a flag data sense circuit built into the priority encoder provided for a CAM block. While a hit signal in the first priority subblock is being encoded, a hit signal in the second priority subblock can be stored in the prefetch circuit. Therefore, the encoding operation is performed without subblock-to-subblock switch time and this makes the encoder best suitable for a large capacity CAM which is required to operate at high speed. Moreover, a semiconductor integrated circuit of the present invention detects the differential current between the current flowing through one signal line and the reference current flowing through the other signal line. Moreover, it can operate as the number detection circuit to detect the number of hit signal in the subblock, and it can operate as the timing control circuit to previously notify the encode termination of the hit signal in the subblock of the encoder described above. Therefore, this semiconductor integrated circuit can allow the encoder to encode very efficiently at high speed. Moreover, a dynamic sense amplifier is able to operate with a great operating margin.