Memory system having a column address counter and a page address counter

Abstract

A memory system which includes a memory array having a column address input and a page address input, addressed by a column pointer and a page pointer; a processor for accessing the memory array with employment of a data bus and an address bus in response to an access instruction; a page register unit coupled to the processor, for storing therein a page address and a first offset address, which are received from the processor via the data bus; a page address counter unit coupled to the page register unit for performing a predetermined calculation to the page address by utilizing the first offset address; a column register unit coupled to the processor, for storing therein a column address and a second offset address, which are received via the address bus from the processor; a column address counter unit coupled to the column register unit, for performing a preselected calculation to the column address with employment of the second offset address; and an address latch unit coupled to the page address counter unit and the column address counter unit, for outputting outputs derived from the page address counter unit and the column address counter unit to the column address input and the page address input of the memory array in order to access the memory array by the processor. Overhead of the process for address calculations to manage the memory system is reduced, so that a high-speed accessing operation is realized.