The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 03, 1998
Filed:
Nov. 22, 1995
Stephen A Smith, Palo Alto, CA (US);
Jafar Naji, Glenbare, CA (US);
Cirrus Logic, Inc., Fremont, CA (US);
Abstract
A method and arrangement for controlling input/output (I/O) operations in a computer system provides multiple PC card controllers but allows legacy software to be used. A PCI bus is coupled to a central processing unit, and an ISA bus is coupled to the PCI bus by a bridge. At least one PC card controller is coupled to the PCI bus and at least one other PC card controller is coupled to the ISA bus. Each PC card controller has at least one socket in which a device is connectable, each socket being separately addressable by the processor at an (I/O) address through the respect PC card controller. Each controller also has a socket pointer register, each socket pointer register being loadable with socket pointer information that uniquely identifies each socket of the controller among all of the sockets of the plurality of controllers in the computer system. Each controller also has an index register and a plurality of data registers, the index stored in the index register pointing to one of the data registers. The index registers of the PC card controllers are updated when the processor writes to an I/O address, without acknowledging the write on the PCI bus. This allows the writes to propagate through the system to lower levels, instead of being stopped by a subtractive decode device. To perform this, each PC card controller compares the socket pointer information with the updated index in the index register. When at least a portion of the socket pointer information matches at least a portion of the updated index, the PC card controller updates with write data the data register pointed to by the index register.