The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 03, 1998
Filed:
Jan. 29, 1997
Katsushi Nagaba, Kawasaki, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
The input pads DQ0 to DQ3 and the input buffers DIB0 to DIB3 are connected to each other by means of the wires La or Lb. In the case where the memory cell array is of the .times.4 bit pattern, the input pads DQ0 to DQ3 are connected to the input terminals of the input buffers DIB0 to DIB3, respectively, via the wires La, whereas in the case where the memory cell array is of the .times.1 bit pattern, one of the input pads, that is, DQ0 is connected to each of the input terminals of the input buffers DIB0 to DIB3 via the wires Lb. The structures from the input buffers DIB0 to DIB3 to the memory cell arrays are the same and common to the .times.4 bit pattern and the .times.1 bit pattern, and therefore an increase in the driving performance of the transistors in the input buffers DIB0 to DIB3 can be suppressed.