The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 03, 1998
Filed:
Jun. 07, 1995
William D Heavlin, San Francisco, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A system and a method for designing, fabricating and testing multiple cell test structures validate a cell library. Each test structure includes a plurality of logic layers where outputs of a logic layer are connected only to the inputs of a succeeding logic layer. In contrast to the conventional design method, mismatches in each logic layer are increased to assure extreme conditions in the test structure. For each logic layer, the number of fan-outs of each output from the previous logic layer is specified, and the number of basic cells in each layer is based on the number of inputs of the test structure. Based on D-optimality and maximum fan-in resolution, an assignment for connecting each fan-out and each fan-in is determined. Alternatively, a design repair algorithm can be used to make such an assignment. Each output of each logic cell in the logic layer is then assigned a length using D-optimality. The predicted propagation delays of a designed test structure are compared to the actual propagation delays of a fabricated test structure. The above is repeated for designing, fabricating, and testing multiple cell test structures to validate the cell library.